The present embodiments relate to circuit design flow and are more particularly directed to including consideration of metastability into the circuit design flow.
Circuit design flow includes at least two general steps. Typically using some combination of hardware and/or software, in a first step the designer creates a functional behavioral model such as by way of example in a register transfer level (“RTL”) design. In this first step, the functionality of the RTL level design is verified. Once the RTL functionality is verified, in a second step the RTL is synthesized into gate level circuitry and the designer performs gate level simulations. In this second step, functional wave timing is examined, which includes analyses of gate delays and interconnect delays.
While the preceding circuit design flow steps have proven workable in numerous contexts, the present inventors have observed various drawbacks, such as in the context of an asynchronous design. Asynchronous paths by definition include signals that pass from one clock domain to another. When this occurs from a first clock domain to a second clock domain, the timing of circuitry operating according to the second clock domain may be disrupted or operate inaccurately due to a signal that is still timed according to the first clock domain. This disruption is particularly evident in the context of a flip-flop in one clock domain that attempts to process a signal from a different clock domain. In this regard, a flip-flop is known in the art to have both a setup and hold time, typically indicated as Tsu and Th, respectively. In general, a window of time is thereby defined that consists of the duration of both Tsu and Th and during that window the clock is expected to transition at the flip-flop; further, for proper operation of the flip-flop, its input data should not transition during this Tsu+Th window, that is, it should not transition during either Tsu or Th. However, if the data input is from one clock domain while the flip-flop is clocked by a different, and hence asynchronous, clock domain, then indeed the data may transition during the Tsu+Th window. If this occurs, it is said that there is either a setup or hold time violation, and as a result the flip-flop enters a state where its output is unpredictable. This unpredictable output, therefore, may be either a binary 1 or 0, and this state is referred to as metastability.
Given the chance and indeed likelihood of metastability, designers at both the RTL and gate level design levels have heretofore been provided certain approaches that the present inventors have observed not to adequately contemplate the reality of metastability. With respect to RTL, it is primarily directed to the presentation or collection of functionality and, thus, has not concerned itself with the concept of timing. Indeed, RTL instead assumes ideal timing with respect to the propagation of signals. As a result, metastability, which often arises from asynchronous connectivity as described above, is not addressed during the RTL design flow. With respect to gate level simulations, circuits from cell libraries are assigned whereby certain circuitry and timing tables may be attributed to different RTL functions. However, for asynchronous paths, prior art gate level simulations in effect permit the violation of timing in that proper timing is assumed not important. Moreover, if the assumption holds untrue or for other reasons, the designer heretofore has the option of designating any desired path as a “false path,” after which it is removed from any test that is imposed during the gate level simulations. Moreover, once designated as a false path, the timing on the path is turned off, negating the whole point of gate level simulations with timing. Instead, precise data capture is assumed to occur. If it is not labeled as a false path and timing is kept, then data on that path is indicated as an “x”. When violation occurs, the effect of that data as it further propagates through the design is no longer meaningful nor analyzed and the simulation will in likelihood be invalidated. Thus, there is no accountability for correct functionality at either the RTL or gate level simulations as to the effects of metastability.
As a result of the preceding, it is not uncommon for integrated circuits to be constructed according to a design that was developed according to the prior art, only to learn after the construction of the device that it does not operate properly due to metastability. In view of this result, there arises a need to address the drawbacks of the prior art as is achieved by the preferred embodiments described below.